Technology has been proposed to three-dimensionally arrange memory cells by making memory holes in a stacked body including insulating layers multiply stacked alternately with electrode layers that function as control gates, forming charge storage films on the side walls of the memory holes, and providing silicon inside the memory holes.
In such a structure, the memory cell of the uppermost layer or the lowermost layer is adjacent to a selection transistor or a back gate transistor which has a structure different from those of the memory cells. Therefore, the patterned configurations and the device characteristics of the memory cells of the uppermost layer and the lowermost layer easily differ from those of the other memory cells which may cause fluctuation of the characteristics of the memory cells as an entirety.